Many computer systems provide a prefetch mechanism by which selected data is loaded into cache memory before it is referenced by a program in order to reduce the time the processor has to wait for data (prefetched “data” refers to both instructions and data). For example, a load instruction typically reads data referenced by a target address into a local processor register. If the referenced data is in cache memory, the processor spends less time waiting for the data. However, if the referenced data is not in cache memory (a “cache-miss” condition), the data is read from memory to the register and also stored in cache memory for subsequent references. In the case of a cache-miss, the processor spends more time waiting than if the data had been present in cache memory. Therefore, when the data is prefetched into cache memory, the waiting by the process is reduced.
Some known prefetch mechanisms attempt during program execution to predict which data to prefetch based on observed program behavior. When the prediction is correct, the processor spends less time waiting for data and therefore has improved throughput. However, when the prediction is incorrect and data is prefetched and not subsequently referenced, the errant prefetch unnecessarily consumes resources of the cache memory and memory bus. To further complicate matters, correctly predicting the data to load is made difficult in some cases because the address from which the data is to be loaded may not be available until it is too late to prefetch data.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.